1. Field of the Invention
The present invention relates to an internal conductor connection structure and a multilayer substrate. In particular, the present invention relates to an internal conductor connection structure capable of increasing a wiring density and to a multilayer substrate.
2. Description of the Related Art
In recent years, technologies for micromachining integrated circuits have dramatically advanced and, thereby, the number of external terminals of the integrated circuit has been increased, so that a pitch between external terminals has been reduced significantly. Recently, integrated circuits are mounted on ceramic substrates primarily by a flip chip bonding system. Pads for flip chip bonding are disposed on the surface of the ceramic substrate. Since the pitch between bonding pads must be reduced in accordance with a reduction of the pitch between external terminals of the integrated circuit, some methods have been proposed up to now.
For example, Japanese Patent No. 2680443 has proposed a ceramic wiring board provided with no bonding pad. The bonding pad is formed by a printing method or the like. When the number of bonding pads is increased, it becomes difficult to form pads by the printing method or the like. Even when bonding pads can be formed, the strength of bonding to the via conductor is weak, and the reliability cannot be ensured. Consequently, in the technology described in Japanese Patent No. 2680443, a ceramic multilayer substrate is produced by using a conductor paste having a firing shrinkage factor smaller than that of a ceramic green sheet and, thereby, a conductor layer (via conductor) in a through hole is allowed to protrude as a bonding pad from the ceramic multilayer substrate. In this manner, printing of the bonding pad is avoided, the strength of bond between the bonding pad and the via conductor is increased and, in addition, a reduction of pitch between bonding pads is realized. However, in Japanese Patent No. 2680443, no consideration is given to the connection structure of the via conductor and the line conductor in the inside of the ceramic multilayer substrate.
On the other hand, Japanese Unexamined Patent Application Publication No. 2001-284811 has proposed a monolithic ceramic electronic component in which a line conductor is provided with a connecting land, and a connection structure of a via conductor and the line conductor is improved. In the case where the via conductor and the line conductor are connected, a ceramic green sheet provided with the via conductor and a ceramic green sheet provided with the line conductor are aligned, and a laminate of the ceramic green sheets is prepared, followed by sintering. An occurrence of an error cannot be avoided in the formation of the via conductor and the line conductor on the ceramic green sheets, and it is difficult to avoid an occurrence of discrepancies between positions of the via conductor and the line conductor in the preparation of the laminate. Therefore, a poor connection between the via conductor and the line conductor tends to occur in the laminate. Consequently, in this technology, the line conductor is provided with a connecting land having a diameter larger than the outer diameter of the via conductor and, thereby, the occurrence of a poor connection resulting from the error and discrepancies between positions is prevented.
Japanese Unexamined Patent Application Publication No. 11-074645 has proposed a method for manufacturing a multilayer ceramic substrate, in which the wiring density can be increased. In this case, as shown in FIGS. 9A and 9B, a connecting land 3 is provided on the lower end of a via conductor 2 disposed in a multilayer ceramic substrate 1, and when via conductors 2 are adjacent to each other, their respective connecting lands 3 are provided in mutually different respective ceramic layers. The via conductors 3 are connected to line conductors 4 through the connecting lands 3. This technology is in common with the technology in Japanese Unexamined Patent Application Publication No. 2001-284811 in that the connecting land 3 is exposed.
In the known technologies described in Japanese Unexamined Patent Application Publication No. 2001-284811 and Japanese Unexamined Patent Application Publication No. 11-074645, since the line conductor or the via conductor has the connecting land, an occurrence of a poor connection resulting from discrepancies between positions of the via conductor and the line conductor, their respective working errors, and the like in the preparation of the ceramic substrate can be prevented by the connecting land. However, there is a problem in that, for example, as shown in FIG. 9A, since a connecting land 3 extends from a via conductor 2 toward an adjacent via conductor 2, a reduction of pitch between the adjacent via conductors 2 is hindered by the amount of the protrusion of the connecting land. That is, when the pitch between the adjacent via conductors 2 is reduced, as shown in FIG. 10, the connecting land 3 and the adjacent via conductor 2 tend to be short-circuited, and delamination tends to occur during firing due to the difference in thermal expansion between the ceramic layer and the connecting land 3. Therefore, at least a clearance for preventing short circuiting and delamination is required between the adjacent via conductors 2, and an extended dimension of the connecting land 3 is further added to this clearance, so that the connecting land hinders a reduction of the pitch between the adjacent via conductors 2.